They then group the items to be sorted into buckets according to their high digits, in linear time, using either a large but uninitialized direct addressed memory or a hash table.
3.
In CPU design, the use of a "'Sum Addressed Decoder "'or "'Sum Addressed Memory ( SAM ) Decoder "'is a method of reducing the latency of the CPU cache access.
4.
As time progressed, even more memory could be added through third-party cards using the same bank-switching slot or, alternatively, general-purpose slot cards that addressed memory 1 byte at a time ( i . e . Slinky RAM cards ).
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