There may also be a memory address register and a memory data register, used to access the main computer storage.
2.
The remaining control signals are self-explanatory and can be understood easily as in "'Example 1 "'where MDR is the bidirectional Memory data register and MAR is the unidirectional Memory Address Register.
3.
For example, the 14-bit address, which could access " 16 K ?8 bits of memory ", needed to be latched by some of this logic into an external Memory Address Register ( MAR ).
4.
A Memory Address Register Storage ( MARS ) Core memory read, clear, or write operation took 2 ?s and each write operation was automatically ( but not necessarily immediately ) preceded by a read or clear operation of the same " register ( s ) " during the 20 ?s memory cycle.
5.
A Memory Address Register Storage ( MARS ) core memory read, clear, or write operation took 1.5 �s and each write operation was automatically ( but not necessarily immediately ) preceded by a read or clear operation of the same " register ( s ) " during the 10 �s memory cycle.
6.
These registers include the " IR " ( instruction register ), " IBR " ( instruction buffer register ), " MQ " ( multiplier quotient register ), " MAR " ( memory address register ), and " MDR " ( memory data register ) . " The architecture also uses a program counter ( " PC " ) to keep track of where in the program the machine is.
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