During a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the address is incremented twice per data phase.
12.
Once one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase.
13.
While the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which 8-bit bytes are to be considered significant.
14.
If a parity error is detected during an address phase ( or the data phase of a Special Cycle ), the devices which observe it assert the SERR # ( System error ) line.
15.
The target deasserts DEVSEL #, driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase.
16.
A data phase with all four C / BE # lines deasserted is explicitly permitted by the PCI standard, and must have no effect on the target other than to advance the address in the burst access in progress.
17.
MNP 4 also introduced "'Data Phase Optimization "', a simple change to the protocol that allowed some of the packet-framing information to be dropped after the link was set up, further reducing protocol overhead.
18.
The data recipient must latch the AD bus each cycle until it sees both IRDY # and TRDY # asserted, which marks the end of the current data phase and indicates that the just-latched data is the word to be transferred.
19.
On clock edge 6, the target indicates that it wants to stop ( with data ), but the initiator is already holding IRDY # low, so there is a fifth data phase ( clock edge 7 ), during which no data is transferred.
20.
Wireless data transfers tend to incur in very significant overheads; to mitigate this W-USB replaces these with the " burst mode data phase ", which groups one or more data packets which reducing packet delimiters and separation gaps, in contrast with the USB rule of one data packet per transaction.
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