11. This was a synchronous private memory bus which allowed for simultaneous memory input / output transfers. 12. This bandwidth is what is referred to as the memory bus and can be performance limiting. 13. Within a year some Sun systems used MBus, another interconnection standard, as a CPU memory bus . 14. These DIMMs are installed in identical pairs in order to match the width of the memory bus . 15. DDR3 ECC bits are used to verify the integrity of the data being sent across memory bus . 16. A bay might contain a processor bus, a shared memory bus , or an I / O bus. 17. Main memory is directly or indirectly connected to the central processing unit via a " memory bus ". 18. Each CMIC ASIC is responsible for managing half of the 280-bit memory bus and the 128-bit system bus. 19. It operated at speeds between 166 and 233 MHz and supported a memory bus up to 66 MHz. 20. It is therefore connected to 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.
