Typically, the reference clock enters the chip and drives a phase locked loop ( "'PLL "'), which then drives the system's clock distribution.
12.
In electronics and telecommunications, "'jitter "'is the deviation from true periodicity of a presumably periodic signal, often in relation to a reference clock signal.
13.
Reference clock jitter translates directly to the output, but this jitter is a smaller percentage of the output period ( by the ratio above ).
14.
However, " clock block " resources can be used to provide different clock signals, either by dividing the reference clock, or based on an external signal.
15.
"' Oregon Scientific, Inc . "'is a manufacturer of electronic products including radio-referenced clocks, home weather stations, public alert monitors, youth learning aids and fitness devices.
16.
A U . 2 solution for PCIe 3.0 x4 could use a modified miniSAS HD cable with PCIe reference clock routed over the sideband of the cable.
17.
In order to provide evenly spaced measurements will the reference clock be divided down to form the measurement rate, triggering the time-interval counter ( ARM input ).
18.
The 8b / 10b encoded sequence embeds periodic edge transitions to allow the receiver to achieve bit-alignment without the use of a separately transmitted reference clock waveform.
19.
However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream.
20.
Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference.
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