21. The 28 / had 1024-bit instruction words. 22. Finally, in long mode ( AMD Opteron onwards ), 64-bit instructions , and more registers, are also available. 23. Each 48-bit word contained two 24-bit instructions . 24. When long mode is operating, 16-bit instructions and virtual x86 mode are disabled and protected mode disappears. 25. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions . 26. Since the x86-64 architecture includes hardware-level support for 32-bit instructions , WoW64 simply switches the process between 32-and 64-bit modes. 27. This required small opcodes in order to leave room for a reasonably sized constant in a 32-bit instruction word. 28. It operates in parallel with the main processor, both processors receiving their instructions from a single 32-bit instruction stream. 29. An instruction is composed of a 6-bit instruction ( conventionally represented in octal ) and a 13 bit address. 30. The processor address bus was now 16 bits and the instruction set consisted of 8, 16, and 24 bit instructions .
