The typical method of utilizing an interrupt vector involves reading its present value ( the address ), storing it within the memory space of the TSR, and installing a pointer to its own code.
22.
This was done despite the first 32 ( INT00-INT1F ) interrupt vectors being reserved by the processor for internal exceptions ( this was ignored for the design of the PC for some reason ).
23.
The first word of the interrupt vector contains the address of the interrupt service routine and the second word the value to be loaded into the PSW ( priority level ) on entry to the service routine.
24.
The " fetch " method loads the PC indirectly, using the address of some entry inside the interrupt vector table to pull an address out of that table, and then loading the PC with that address.
25.
Interrupts are vectored : a card requesting an interrupt has its interrupt vector read by the IFP . In this way, the interrupts from all I / O cards in the system can be distinguished with no ambiguity.
26.
With its total control, this program is not required to ever call the BIOS again and may even shut BIOS down completely, by removing the BIOS ISR vectors from the processor interrupt vector table, and then overwrite the BIOS data area.
27.
The processor has a special register ( ) to store both the physical base address and the length in bytes of the IDT . When an interrupt occurs, the processor multiplies the interrupt vector by 8 and adds the result to the IDT base address.
28.
There are also two similar instructions, ( E ) FLAGS register value on the stack, then performs a far call, except that instead of an address, it uses an " interrupt vector ", an index into a table of interrupt handler addresses.
29.
While in principle an extremely short interrupt handler could be stored entirely inside the interrupt vector table, in practice the code at each and every entry is " JMP address " where the address is the address of the interrupt service routine ( ISR ) for that interrupt.
30.
On the PC, the BIOS ( and thus also DOS ) traditionally maps the master 8259 interrupt requests ( IRQ0-IRQ7 ) to interrupt vector offset 8 ( INT08-INT0F ) and the slave 8259 ( in PC / AT and later ) interrupt requests ( IRQ8-IRQ15 ) to interrupt vector offset 112 ( INT70-INT77 ).
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