21. Tiers 7 and 8 will each have a 256-bit memory bus and will be marketed as 4K gaming. 22. The memory bus connects the northbridge and RAM, just as the front-side bus connects the CPU and northbridge. 23. It is also impractical to manufacture a single chip with more than two DDR memory buses ( channels ). 24. Similar to the memory bus , the PCI and AGP buses can also be run asynchronously from the front-side bus. 25. Accordingly, Nvidia cut the memory bus to 128 bit on GM107 from 192 bit on GK106, further saving power. 26. Tier 4, the weakest tier in the 400 series, will lack the RX prefix and feature a 64-bit memory bus . 27. The memory bus is 40 bits wide, with 32 bits used for data and four bits used to for byte-parity. 28. Some microcontrollers use a Harvard architecture : separate memory buses for instructions and data, allowing accesses to take place concurrently. 29. The accelerator board was famous for its high performance due to its 64 bit wide memory bus and PowerPC 604e processor. 30. It had 128-to 512-bit memory bus which operated at 83 MHz, yielding a maximum bandwidth of 5, 312 MB / s.
