This comes at the cost of dividing the memory bus into high speed and low speed segments that cannot be accessed at the same time for reads, because the L2 / ROP unit managing both of the GDDR5 controllers shares the read return channel and the write data bus between the GDDR5 controllers.
22.
That reminds me of another gimmick during my bad-old teenage days . ( I've since reformed . ) We'd go to a nearby pay phone and stuff tissues up the coin return channel so that when someone ( not us ) got a busy signal or no answer and hung up, no coin would be returned.
23.
This comes at the cost of dividing the memory bus into high speed and low speed segments that cannot be accessed at the same time unless one segment is reading while the other segment is writing because the L2 / ROP unit managing both of the GDDR5 controllers shares the read return channel and the write data bus between the two GDDR5 controllers and itself.
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