The technique sees common usage in software exploits, where it is used to direct program execution when a branch instruction target is not known precisely.
32.
The solution eliminates all unaligned free-branch instructions inside a binary executable, and protects the free-branch from being used by an attacker.
33.
Apart from eliminating the branch instructions themselves, this preserves the fetch / decode / execute pipeline at the cost of only one cycle per skipped instruction.
34.
Once again assuming a uniform distribution of branch instruction placements, 0.5, 1.5, and 3.5 instructions fetched are discarded.
35.
Instruction decoding and register reads occur during stage two, and branch instructions are resolved as well, leading to a one-cycle branch mispredict penalty.
36.
Flow of control, for example, can be managed by the use of a label ( a colon followed by a string ) and the branch instruction b.
37.
Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip ( with the opposite condition ) followed by an unconditional branch.
38.
The intermediate sync points are automatically triggered at every n'th taken branch instruction, and are also explicitly inserted into long loop bodies by all NonStop compilers.
39.
Multiple ( local ) literal pools are typically used only for computer architectures that lack branch instructions for long jumps, or have a set of instructions optimized for shorter jumps.
40.
With store buffering, stores can execute ahead of exception-causing or unresolved branch instructions, buffering their data in the store queue but not committing their values until retirement.
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